The hardware RNG of the VIA PadLock Data Encryption Engine is particularly important for embedded systems, as it does not rely on less random seed data such as keystroke timing or mouse events typically used to seed software-based RNGs (called pseudorandom number generators).
Integrating the RNG directly onto the die of the microprocessor makes it much more difficult for an attacker to probe or influence, providing greater assurance to end-users.
The new VIA C3 is based on the highly efficient CoolStream architecture that is specifically designed to minimize power consumption and optimize heat dissipation - while reducing overall system noise. Offering a typical design power of just over 10W and a maximum design power of 15W at 1GHz, the new VIA C3 requires minimal cooling enabling a new wave of stylish, quietrunning, small form factor system designs helping to create a healthier and more stressfree working and living environment.
When coupled with the VIA Apollo CLE266 chipset, the VIA C3 delivers performance increases of up to 20% over the current version of the VIA C3 processor in mainstream productivity applications and up to 73% for 3D graphics applications. With its highly efficient design, the new VIA C3 also runs up to 40% faster clock-for-clock than the Intel® Pentium®4 Celeron processor making it the most efficient native x86 processor available today.

Ultra Low Power, Low Heat and Low Noise
With a maximum design power of just over 20 watts at 1.4GHz, the VIA C3 runs extremely cool and delivers very low levels of energy consumption. This not only makes it the ideal solution for powering a wide variety of low profile, small form factor PCs, but also enables very low noise system design implementations that are necessary for the emerging generation of Personal Electronics devices for the living room.

World's Fastest Advanced Native x86 Processor Security Engine
To address the growing need among corporate, government, and home users to protect sensitive data on their connected devices, the C5P Nehemiah core of the VIA C3 processor incorporates advanced on-die security features that make up the VIA PadLock Security Engine, featuring the VIA PadLock ACE (Advanced Cryptography Engine) and the VIA PadLock RNG (Random Number Generator).

Security applications that leverage the military-grade capabilities of the VIA PadLock Security Engine can be deployed quickly and easily across a broad range of devices including PCs, thin clients, set top boxes, home digital entertainment centers, point of sale terminals, and intelligent network routers in a wide variety of wired and wireless networking environments. Potential usage scenarios include Virtual Private Networks (VPNs), Corporate Peer to Peer Networks with restricted access for sensitive projects, and Home Wireless Networks.

Platform for Innovation
With its industry leading low power consumption, exceptional application performance, rock solid reliability, and robust security features, the VIA C3 is unleashing a new wave of innovation in secure, stylish, quiet running small form factor systems that are expanding the reach of x86 architecture into exciting new market segments, such as Personal Electronics. When coupled with the VIA CN400, the first chipset in the world to feature integrated Hardware MPEG4 and MPEG2 acceleration, the VIA C3 is the ideal solution for powering an almost unlimited variety of digital media entertainment devices for the home, the car, hotels, and countless other locations.

The VIA C3™ processor in Enhanced Ball Grid Array (EBGA) packaging is based upon a unique internal architecture and is manufactured using advanced 0.15µ or 0.13µ CMOS technology. The C3 architecture and process technology provide a highly compatible, high-performance, low-cost, and low-power solution for the desktop PC, notebook, and Internet Appliance markets. The VIA C3 processor in EBGA is available in several MHz versions.
When considered individually, the compatibility, function, performance, cost, and power dissipation of the VIA C3 processor family are all very competitive. Furthermore, the value added from the advanced EBGA packaging includes remarkable compactness, cost efficiency and excellent thermal characteristics. The VIA C3 package in EBGA represents a breakthrough combination for enabling high-value, high-performance, low-power, small form factor x86-based solutions. When considered as a whole, the VIA C3 processor family in EBGA offers a peerless level of value.

Basic Features
The VIA C3 processor family in EBGA currently consists of two basic models with several different MHz versions. Due to their low power dissipation, either model is ideally suited for both desktop and mobile applications.
These chips can also be divided into two categories: “S” versions are clock multiplier selectable ; EBGA VIA C3 processors that lack the “S” designation are multiplier fixed. All versions share the following common features:
- A proprietary Enhanced Ball Grid Array (EBGA) package that shares with Socket 370 processors features such as bus protocol and electrical interface
- Seamlessly software compatible with the thousands of available x86 software applications
- MMX-compatible instructions for enhanced media performance
- AMD-compatible 3DNow! Instructions for turbocharging games, photo processing and media applications
- Two large (64-KB each, 4-way) on-chip Level 1 caches
- 64-KB Level 2 victim cache
- Two large TLBs (128 entries each, 8-way) with two page directory caches
- Unique and sophisticated branch prediction mechanisms
- Bus speeds up to 133 MHz and 200MHz
- Extremely low power dissipation
- Very small die (52 mm2 in TSMC 0.13µ technology)
- Compact and economical EBGA packaging with excellent thermal dissipation characteristics

Compatibility
The VIA C3 in EBGA packaging shares much with it conventionally packaged siblings. “Standard” VIA C3’s can plug into existing Socket 370 motherboards and can operate without requiring changes to the system hardware (with one theoretical difference discussed in the next paragraph). No special jumpers or different board wiring is required. In most cases, however, a special BIOS is needed. Currently, BIOS support for the VIA C3 is available from Award, AMI, Phoenix, and Insyde.
The VIA C3 requires external termination of bus signals. Physical and bus compatibility is covered in more detail in Section 4 of this datasheet.
Obviously the VIA C3 in EBGA packaging will not fit into a Socket 370 motherboard since the CPU is mounted directly to the motherboard. By eliminating the need for a CPU socket, the manufacturing costs are reduced while elevating the intrinsic value of the motherboard. The excellent thermal dissipation characteristics of the EBGA package combined with the C3’s class leading low power requirements facilitate the use of small and cheap CPU cooling solutions – even fanless designs are possible.
The VIA C3 supports 3DNow! instructions. The VIA C3 does NOT support multiple processors. These functions are defined as optional by, and are identified to software via, the CPUID instruction. The VIA C3 in EBGA carefully follows the protocol for defining the availability of these optional features. Both the additional and omitted optional features are covered in more detail in Section 3 of this datasheet.
To verify compatibility of the VIA C3 in EBGA with real PC applications and hardware, VIA has performed extensive testing of hundreds of PC boards and peripherals, thousands of software applications, and all known operating systems.

The VIA C3 in EBGA architecture can be either that of the VIA C3 Samuel 2 or the VIA C3 Ezra. The C3, formerly known as the VIA Cyrix III, is different from any other x86 processor architecture. This unique processor design provides a significantly smaller die size using less power than any other x86 CPU. The VIA C3 EBGA features cores that improve performance (MHz and CPI) and further reduces die size and power over the base VIA C3 Samuel. (The major differences between the VIA C3 Samuel processor and the VIA C3 Ezra are highlighted in the descriptions below.) For Nehemiah architecture, please refer to the C3 Nehemiah datasheet.
The VIA C3 architecture is based on, and directly exploits, basic “facts” about the current x86 market, applications, and bus environment. While seemingly straightforward, these concepts are not exploited in other processor architectures. The major concepts that shape the VIA C3 architecture are:

- Only a few instructions dominate x86 instruction execution time. On typical applications, over 90% of instruction execution time is due to a handful of basic x86 instructions. Most x86 instructions have no significant impact on performance.
The VIA C3 design optimizes performance of the most important x86 instructions while minimizing the hardware provided for the little-used x86 functions (infrequently used x86 instructions are primarily implemented in microcode). The resulting instruction execution speed of highly used instructions is as good or better than comparable processors. For example, the VIA C3 executes x86 load-ALUstore instructions in only one clock as compared to several clocks on other processors. The execution time of little-used instructions is impacted to reduce die size, but this has no effect on real application performance.

Improving clock frequency has higher leverage than improving CPI. The result of advanced computer design approaches over the last few years has been that the improvements in cycles-perinstruction (CPI) often impact MHz improvements, and certainly impact die size. Our belief is that the best way to improve total performance and keep a small low-power die is to improve MHz.
Thus, the VIA C3 family architecture provides improved performance by optimizing MHz via a 12-stage pipeline while maintaining a good CPI. Complex CPI-driven features such as out-of-order instruction execution are not implemented because they (1) impact MHz, (2) require a lot of die area and power, and (3) have little impact on real performance since… (the next point)

- Memory performance is the limiting CPI performance factor. In modern PCs, the processor bus is slow compared to the internal clock frequency. Thus, off-chip memory-accesses dominate processor CPI as opposed to internal instruction execution performance.
The VIA C3 addresses this phenomenon by providing many specific features designed to reduce bus activity: large primary caches, large TLBs, aggressive prefetching, an efficient level-2 cache (new to the VIA C3 Samuel 2 and Ezra), and so forth.

- Different market segments have different workload characteristics. The hardware, operating systems, and applications used in our target market (low-end desktop and mobile PCs) have different technical characteristics than those in the high-end, workstation, or server market.
The VIA C3 family exploits these differences by implementing very specific design tradeoffs, providing high performance with low cost in the target environments. These optimizations are based on extensive analysis of actual behavior of target-market hardware and software.

- Small is beautiful. VIA C3 processors are highly optimized for small die size. In addition to the obvious cost benefits, this small size reduces power consumption and improves reliability.

More information : www.via.com.tw